Freescale Semiconductor /MKE14D7 /SIM /SCGC6

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCGC6

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RESERVED)RESERVED 0 (0)DMAMUX 0 (RESERVED)RESERVED 0 (0)PIT 0 (0)CRC 0 (0)PDB0 0 (0)PDB1 0 (0)PDB2 0 (0)PDB3 0 (0)FTM0 0 (0)FTM1 0 (0)FTM2 0 (0)FTM3 0 (0)RTC 0 (RESERVED)RESERVED 0 (0)TSI 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (0)PORTA 0 (0)PORTB 0 (0)PORTC 0 (0)PORTD 0 (0)PORTE 0 (RESERVED)RESERVED 0 (0)ADC0 0 (0)ADC1 0 (0)ADC2 0 (0)ADC3 0 (RESERVED)RESERVED

DMAMUX=0, PORTB=0, TSI=0, PDB0=0, ADC2=0, PORTC=0, PIT=0, PORTD=0, ADC0=0, PDB3=0, PDB2=0, PORTE=0, ADC3=0, FTM0=0, FTM3=0, ADC1=0, CRC=0, PORTA=0, FTM1=0, FTM2=0, RTC=0, PDB1=0

Description

System Clock Gating Control Register 6

Fields

RESERVED

no description available

DMAMUX

DMAMUX Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

RESERVED

no description available

PIT

PIT Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

CRC

CRC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PDB0

PDB0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PDB1

PDB1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PDB2

PDB2 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PDB3

PDB3 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

FTM0

FTM0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

FTM1

FTM1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

FTM2

FTM2 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

FTM3

FTM3 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

RTC

RTC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

RESERVED

no description available

TSI

TSI Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

RESERVED

no description available

RESERVED

no description available

PORTA

Port A Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTB

Port B Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTC

Port C Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTD

Port D Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTE

Port E Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

RESERVED

no description available

ADC0

ADC0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

ADC1

ADC1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

ADC2

ADC2 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

ADC3

ADC3 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

RESERVED

no description available

Links

()